Integrated circuit bipolar random access memories (RAMs) have found widespread use in high speed digital computers as intermediate "scratch-pad" memories or "cache" memories. The basic requirements on such bipolar RAMs has been that they provide relatively high speed operation at a relatively low cost, since such memories must interface between the high speed (high cost) arithmetic section of digital computers and the slower main memories, which must provide low cost storage for the storage of the programs and data being processed.
A widely used flip-flop memory cell for such bipolar RAMs includes two cross-coupled inverters each having a resistor as a load device and a dual emitter transistor as a switching device. Two emitters, one from each transistor, are coupled together and connected to a standby current source and also to the two corresponding emitters of each of the other flip-flop memory cells in the same row. The other two emitters each are coupled to corresponding sense-write conductors which are shared with the other flip-flop memory cells in the same column. The sense-write circuits known in the art utilize the interaction between the internal collector node voltage of a selected flip-flop storage cell and a reference threshold voltage generated externally from the flip-flop memory cells to set the state of a differential pair of transistors in the sense amplifier portion of the sense-write circuit to produce an output differential sense voltage. The main shortcoming of such sense-write circuits is that the reference threshold voltage must be selected so that it lies between the two collector node voltages of the selected flip-flop storage cell. The relationship between the magnitude of the differential memory cell collector voltage and the reference voltage must be such that the "on" side flip-flop storage cell transistor base voltage is greater than the threshold reference voltage by an amount sufficient to ensure differential switching and the reference threshold voltage must be greater than the "off" side memory cell transistor base voltage by a similar amount. This implies that the magnitude of the differential memory cell collector voltage must be at least twice that which is required for differential switching. In addition, the magnitude of the differential memory cell collector voltage must be still greater by an amount sufficient to allow for tolerance variations in the memory cell collector voltages, which are caused mainly by variations in tolerance of the memory cell load resistors. In order to increase the tolerance of the load resistors, it is necessary because of photolithographic limitations in the present manufacturing methods to increase their physical size. This, of course, reduces the number of memory cells per chip, increasing the chip size, and hence, the cost per bit of memory storage. Further, performance is impaired due to the increased parasitic capacitances associated with an increase in physical size. Also, the necessity of increasing the magnitude of the difference between the flip-flop memory cell collector voltages increases the memory cell time constants, increasing the time required for the cell to switch states during a write operation.